Todays SOC designs are architected top-down and designed bottom-up, meaning that the design specifications are dictated from the top level requirements and budgeted downwards to lower level blocks. Once lower level blocks are designed and completed the resulting block level characteristics are integrated upwards, or bottom-up for final SOC assembly.
Much attention has been devoted to functional aspect of the top-down to bottom-up design approach. Many tools are available in designers’ arsenal to validate the functional aspect of the design from simulators, linters, to formal equivalency checkers, etc. As a result functional design specification are propagated to lower level blocks and once block level design is complete, the performance metrics are propagated back to the top for functional validation. Such metrics however are missing when it comes to timing data, which for the most part are ignored from the functional simulation and it is left to the designer to “later” specify and capture them in the form of timing constraints. The process of the timing constraints definition as well as downward or upward propagation of such information is basically manual and solely relies on designer memory, skill, and intelligence with little automation aid to help in validating the information once captured.
The result of the gap in timing data propagation and validation has significant impact on tape-out schedules and accuracy of static timing analysis which if it does not result in a failed chip it will certainly result in much delay in schedules. Today Once the design architecture is finalized and the timing data is communicated to the designers it is up to the designer to captured timing metrics of a block correctly in a SDC “file”. The task of designers for all subsequent levels of hierarchy is to translate and propagate the timing information from the lower level SDC “file” to a higher level “file”. This error prone process if for the most part manual and very time consuming.
Excellicon has fully automated the timing constraints propagation process, while addressing transformation of timing data at all layers of hierarchy in the context of the overall design. Whether designer is starting with existing timing constraints or wishes to automatically generate the timing constraints, he will be able to seamlessly propagated timing information from architectural specification stage to the lower level blocks and back to the top level for final chip integration with out much manual work or need for user intervention. Once the tools initially analyze the design then the timing information is propagated throughout the entire design at any layer of hierarchy and for any mode of operation designated by the design architecture.
The impact is significant. First the manual and error prone work is eliminated, adding to the efficiency and accuracy of the process. Second the time it takes to complete such tasks has been shrunk down to minutes as opposed to weeks. Finally the timing information for any layer and all layers of hierarchy is updated instantaneously as lower level design information is updated for every rev of the lower level blocks or any intermediate layer of hierarchy. There is no need for the designer to “redo” all the work over and over every time a block changes its timing metrics. Taking such degree of automation into account, users are the enabled to generate and manage as many timing constraints files as necessary for their design in accordance to the process node requirements form manufacturer.
Done Once! Done Right!