Socionext paper presented at 2016 DAC reports significant time savings using Excellicon products.

2.2 – IP Timing Constraints Promotion Challenges (A method to automatically generate SoC Timing Constraints)

65.11 – An Effectual Approach of Timing Constraints Promotion and Demotion

Checkout how Excellicon is changing the way the timing constraints are done, as show cased in Chip Design Magazine

excellicon_article_chipdesign_2016-1

Or click on the link to Chip Design magazine

http://eecatalog.com/chipdesign/2016/06/09/migrating-from-manual-and-validation-based-timing-constraints-development-to-automated-synthesis-model-extracted-from-design/